SLVS-EC3 RX IP

for AMD FPGAs

    Product Specifications

    Key Specifications

    Item Specifications
    SLVS-EC Version 3.1 Compliant
    Lane 1, 2, 4, 6, 8
    RAW Bit Depth 8, 10, 12, 14, 16
    Line Length 4–65,532 (multiples of 4)
    Input Data Width 32, 64
    Coding 8B10B, GCC
    CRC Supported
    ECC Supported
    Baud Rate Up to 12.5 Gbps per lane
    Multi-Stream Not Supported
    Output Signals Pixel Data,
    Sync. Signals,
    Packet Header, etc.
    Devices AMD 7-Series,
    AMD UltraScale,
    AMD UltraScale+

    Resource Usage

    Resource usage for the SLVS-EC3 RX IP varies depending on factors such as the input data bus width, maximum number of lanes, and the presence or absence of error correction capabilities. The table below shows resource usage for each configuration (Kintex UltraScale+, Vivado 2025.2).

    Input data bus width = 32 bits/lane (ECC support indicated in parentheses)

    Resource 1-Lane 2 Lanes 4-lane 6 Lanes 8-Lane
    LUT 3077 (4919) 4919 (6692) 8,743 (10,914) 14,429 (19,871) 18,081 (23,592)
    FF 1602 (3654) 2,418 (4,377) 4,333 (7,044) 6,781 (11,137) 8394 (12,767)
    BRAM 0 (4.5) 0(4.5) 0(7.5) 0 (13.5) 0(13.5)

    Input data bus width = 64 bits/lane (ECC support indicated in parentheses)

    Resource 1 Lane 2 Lanes 4 Lanes 6 lanes 8-lane
    LUT 4718 (7323) 8083 (10755) 16,983 (22,081) 28,884 (40,520) 35,866 (47,509)
    FF 2848 (5558) 4,644 (7,353) 8,908 (13,270) 14,233 (22,355) 17,864 (25,994)
    BRAM 0 (7.5) 0 (7.5) 0 (13.5) 0(34) 0(34)

    Demonstration Environment

    We offer a reference design that utilizes Sony’s IMX901 sensor board, AMD’s KCU105 evaluation board, and a relay board to connect the two. In this environment, you can demonstrate RAW10 and RAW12 at up to 4 lanes. Customers are free to customize the reference design as needed.We can also propose other configurations based on your specific requirements.

    rx3_img

    Product Brochure

    Introducing the SLVS-EC3 RX IP