SLVS-EC RX IP
for AMD / for EFINIX
SLVS-EC RX IP Overview
At CIS, we have developed an IP that specializes in extracting pixel data from byte data received via an FPGA’s high-speed transceiver, resulting in lower resource consumption.Although FPGA internal clock and data bus configurations vary depending on the application, combining this IP with your logic allows you to optimize total resource usage. Additionally, it now supports payload error detection and error correction (optional).
Product Specifications
Specifications Table
| SLVS-EC Version | 2.0 Compliant |
|---|---|
| Lane | 1, 2, 4, 6, 8 |
| Raw Format | 8, 10, 12, 14, 16 |
| Line Length | 4–∞ (default 65532) |
| CRC | Supported |
| ECC | Supported (optional) |
| Baud Rate | Grade 1–3 |
| Multi-Stream | Not supported |
| Output Signals | Pixel data, synchronization signals, header information, etc. |
Resource Usage
One of the key features of CIS’s SLVS-EC Receiver IP is its low resource consumption. While this IP allows you to dynamically adjust the number of SLVS-EC lanes—which affects resource consumption—you can further reduce resource usage by limiting the maximum number of lanes used or by selecting a fixed lane configuration.The following table shows the resource usage for each configuration (Kintex Ultrascale+, Vivado 2023.1). Please contact us for information on resource usage when using other devices or tools.
Variable Lanes (ECC support indicated in parentheses)
| Resource | Max. 1 Lane | Max. 2 Lanes | Max. 4 Lanes | Max. 4 Lanes | Max. 8 Lanes |
| LUT | 1311 (2748) | 1,450 (2,879) | 2005 (4127) | 4102 (6966) | 4300 (7169) |
|---|---|---|---|---|---|
| FF | 794 (2299) | 854 (2360) | 1201 (3091) | 1,803 (4,422) | 1922 (4539) |
| BRAM | 0 (2.5) | 0 (2.5) | 0 (2.5) | 0 (3.5) | 0(3.5) |
Fixed Lanes (ECC support indicated in parentheses)
| Resource | 1 Lane | 2Lane | 4-Lane | 6-lane | 8-lane |
| LUT | 1147 (2593) | 1268 (2684) | 1562 (3660) | 2696 (5510) | 2513 (5605) |
|---|---|---|---|---|---|
| FF | 738 (2246) | 826 (2,329) | 1150 (3036) | 1,690 (4,295) | 1876 (4484) |
| BRAM | 0 (2.5) | 0 (2.5) | 0 (2.5) | 0 (3.5) | 0(3.5) |
Supported Devices
AMD 7-Series, AMD Ultrascale, AMD Ultrascale+, Efinix Titanium, Efinix Topaz
Please contact us regarding any customization requests.
Demonstration Environment
CIS provides a interface board for connecting Sony's IMX420 sensor board to AMD's evaluation board, as well as reference designs for each evaluation board.For example, when using the AC701, you can perform Raw8, Raw10, and Raw12 demonstrations with up to 2 lanes; when using the KCU105 and ZCU106, you can perform these demonstrations with up to 8 lanes. Customers are free to customize the reference designs as needed.
We also provide a demonstration environment for Efinix’s Ti375N1156 evaluation board.
Product Brochure
Introducing the SLVS-EC RX IP